Technical Program

Preliminary Technical Program

April, 12th, 2023

Imaging Sensors
Chairman: Kofi Makinwa (TU Delft)

  • Fridolin Michel, Charalambos Andreou and Massimo Rigo (ams OSRAM, Switzerland)
    Photon Counting CT Detectors for Medical Imaging
    Computed Tomography (CT) is the foremost medical imaging technique in cancer screening, injury detection and cardiac scans. Classical CT is based on scintillator X-ray conversion materials that allow fast scanning with 3D reconstruction, but only provide black and white images and expose patients to a significant and potentially harmful X-ray dose. Emerging photon counting detectors can provide high-resolution color (spectral) images with a much lower radiation dose. This talk introduces photon counting detectors and describes the topology and design of a CMOS detector chip that will serve as the main platform for next generation CT products at ams OSRAM.
  • Ahmed Faisal and Furqan Muhammad (Infineon Technologies, Austria)
    High-Performance SiGe FMCW Radar Demonstrators at 120 GHz and 240 GHz
    In this work, we present fully-integrated FMCW radar transceivers working in the D-band and WR-03 band, as well as their corresponding radar/imaging demonstrators. Both transceivers have high efficiency and bandwidths, with differential output powers of both D-and WR-03 band in excess of 10 dBm. By combining two D-band transceiver chips, a MIMO system with two transmitters and four receivers is constructed using waveguide antennas. This MIMO radar is used for synthetic aperture radar imaging. The 240-GHz SoC FMCW radar can be combined with an RF front-end via an interposer, resulting in a highly compact system. The resulting demonstrator was successful in sensing targets at distances of up to 2.5 m. Overall, this work represents a significant advancement in the field of fully-integrated FMCW radar transceivers, with high performance and power efficiency.
  • Leonardo Gasparini (FBK, Italy)
    Single-Photon Imagers for Time-Resolved Applications
    Arrays of single-photon avalanche diodes (SPADs) are well suited for time-resolved applications in biomedical, consumer, automotive and scientific applications. This talk will cover the design of interface circuits for SPADs, including quenching circuits supporting dynamically adjustable excess bias voltages, correlation detectors for noise suppression, area efficient in-pixel time-to-digital converters, and circuits that exploit data sparsity to achieve high frame rates with a limited impact on power consumption. These circuits will be discussed in the context of three silicon-proven designs: a 64×64 flash-LiDAR sensor, a 224×227 SPAD imager with reconfigurable pixels and a 32×32 imager that achieves observation rates up to 1 MHz.
  • Michiel Pertijs, Yannick Hopf and Peng Guo (TU Delft, The Netherlands)
    Pitch-Matched Integrated Circuits for Ultrasound Transducer Arrays
    While medical imaging using ultrasound is an established field, technical advances are enabling a range of new ultrasound imaging devices and new use cases. Examples include catheters with 3D imagers, and wearable devices for monitoring and diagnostic applications. Compared to conventional probes, which contained little or no electronics, these new devices are co-integrated with pitch-matched circuitry that interfaces with the many transducer elements (typically 1000+) needed for real-time 3D imaging. This talk will discuss the challenges associated with the design of such circuits, focusing on strategies for channel-count reduction, beamforming and digitization. The talk will include examples of designs with state-of-the-art performance in terms of power consumption, channel reduction and integration density.
  • Frans Widdershoven (NXP Semiconductors and TU Delft, The Netherlands)
    Pixelated Capacitive Sensors for Embedded Multi-Sensing
    Autonomous smart IoT end-nodes need sensors to interact with their environment. Pixelated Capacitive Sensor (PCS) technology provides a highly flexible and scalable true CMOS-compatible platform for embedding a variety of late-definable sensor functions in the same standard CMOS chip, e.g. a microcontroller. This enables designing a variety of tiny low-power smart Edge-IoT applications without expensive upfront investments in modifying precious CMOS processes with long lead times. The PCS technology and its underlying theory will be explained and illustrated with a number of designs in standard CMOS processes.

April, 13th, 2023

Power Management
Chairman: Andrea Baschirotto (University of Milano-Bicocca)

  • Giovanni Frattini (Analog Devices, Italy)
    Integrated Isolated Power Conversion: Challenges and Opportunities
    The talk will discuss the trends of integration of power management circuits and their implications: the advantages that integration offers and the challenges it poses. Specifically, the domain of isolated power conversion will be addressed and a design example will be shown, with focus on the shift in design techniques required to miniaturize a transformer and the circuit to drive it so that the entire solution can fit in a conventional semiconductor package. Design and performance tradeoffs will also be discussed.
  • Francesco Pulvirenti (STMicroelectronics, Italy)
    Design Solutions for Power Converters from System in Package to Monolithic GaN Technology
    Improving power conversion efficiency is an important goal in a world with increasing energy demand. Indeed, in recent years, research has focused on overcoming the limitations of silicon devices to improve the performance of integrated electronic systems. A power system with smaller size, higher switching frequency, and lower power consumption than existing products is in fact necessary to meet future market demands. In addition, portable devices are becoming smaller and lighter, making heat dissipation more difficult. The topic of the presentation focuses on design solutions ranging from System in Package to monolithic ones in the emerging gallium nitride technology, primarily conceived for power converters, such as adapters and chargers, where power density is a key parameter.
  • Francesco Rezzi (Inventvm, Italy)
    Comparison of Standard Switching-Inductor Converter with Hybrid Topologies
    Hybrid converters have recently gained the attention of the design community on the quest of improved efficiency. Hybrid converters combine switched capacitor with a switched inductor conversion stages trying to exploit the advantages of both and reduce their limitations. However, pros and cons of these converters must be carefully considered accounting for their increased complexity and cost also due to the need of extra passive components. The presentation will focus on the detailed comparison and implementation of the 3-level buck converter vs. the classic 2-level switched inductor converter and provide guidance for a correct comparison of the two solutions. It will also illustrate an overview of other possible hybrid topologies.
  • Filip Tavernier and Tuur Van Daele (KU Leuven, Belgium)
    Design and Implementation of a High-Voltage DC-DC Converter for Large Conversion Steps in CMOS
    There is a trend toward using high-voltage sources in various applications, such as cloud computing, industrial automation, and electric vehicles. These high voltage levels are necessary to meet the increasing power demands and are going up to 400 V and beyond for some applications. However, low-power applications, such as actuators, microcontrollers, and sensors, still operate at lower voltages. To bridge this voltage gap, a high-voltage DC-DC converter is required to perform a large conversion step. Conventional approaches require bulky inductors or transformers which cannot be efficiently integrated onto a single chip. The complete integration can potentially significantly reduce costs and enable compact solutions. This paper discusses handling large voltages in a single-chip solution and minimizing the parasitic effects. Moreover, it will showcase how to apply these guidelines by discussing the implementation of a fully integrated 400 V-to-12 V DC-DC converter in a high-voltage CMOS process.
  • Nicolò Zilio (Infineon, Austria)
    Design, Control, and Implementation of Fully-Monolithic Hybrid Power Converters
    Among recent trends in power electronics, monolithic integration of power converters became in focus with particular interest towards hybrid DCDC converters. These converters offer multiple advantages, from decreased voltage stress on the switches to reduced size of external components, leading to smaller PCB footprint, volume, and weight. Hybrid power converter integration brings analog design challenges due to the presence of multiple floating supply rails, fast gate drivers and level shifters. Moreover, ensuring the balancing of flying capacitors leads to additional complexity in the feedback loop architecture. A comparison among different control techniques ranging from voltage to current mode control is provided, both in analog and digital domain. Special attention is dedicated to flying capacitor balancing techniques. A practical implementation of a 28-to-3.3 V 2 A fully monolithic 3-level buck converter in 130 nm HV-CMOS is shown including experimental results.
  • Gwilym Luff (Renesas, UK)
    Recent Developments in SISO Buck-Boost Converters
    Over the last decade single-inductor, Single-Input, Single-Output buck-boost DC-DC converters have become a mainstream power conversion subsystem with many applications in battery powered devices. Starting with the power switch topology, we develop the switch sequences cycles required to regulate output voltages above the input voltage with Boost cycles, below with buck cycles or approximately equal with buck-boost cycles. An overview and classification of controller types shows several different approaches taken to managing transitions between the three power conversion modes. With this background we follow the design choices behind a 200 nA Iq buck-boost converter design for IoT designs through to silicon results. Input and output voltages span 1.8 to 5.5 V for common battery chemistries, while a 2x106 dynamic range from 2000 nA Iq to 400 mA full inductor current satisfies primary battery or storage capacitor applications. Fully hysteretic control of switching and mode transitions improves transient regulation with small off chip capacitors for an 11mm2 total PCB area

April, 14th, 2023

PLLs and Frequency Synthesizers
Chairman: Bram Nauta (University of Twente)

  • Bogdanv Staszewski (University of Dublin, Ireland)
    Beyond All-Digital PLL for RF and Millimeter-Wave Frequency Synthesis
    The past several years has seen proliferation of all-digital phase-locked loops (ADPLL) for RF, mm-wave and high-performance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also exhibits advantages of better performance, lower power consumption, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated using ‘free’ but powerful digital logic. After covering the fundamentals of ADPLL, the talk will quickly venture into the future of mm-wave frequency synthesis: charge-sharing locking (CSL). The idea is that the capacitor of the LC tank itself will be periodically charge-shared with another capacitor charged by a DAC to a voltage that is expected from a waveform at that particular time point, resulting in an instantaneous phase correction. The resulting voltage change will be detected and used to correct the DCO frequency. This results in a great simplification of circuitry and consumed power while delivering sub-100fs integrated jitter.
  • Xiang Gao (Zhejinang University, China)
    Low Jitter Fractional-N PLL with Phase Detection and Quantization Noise Cancellation in the Voltage Domain
    Conventional PLLs detecting phase error in the time domain using a phase frequency detector often suffer from poor in-band phase noise due to the limited phase detector (PD) gain. The (Sub-)Sampling PLL is becoming a popular low jitter PLL architecture because it can achieve a high PD gain and thus low in-band noise by detecting phase error in the voltage domain. However, the high gain SSPD has a limited linear detection range, which is a challenge in fractional-N operation, with large quantization noise even in phase locked state. This talk will discuss the principal and recent development of the sub-sampling PLL, and then present techniques to realize phase detection and quantization noise cancellation, both in the voltage domain, thereby enabling the fractional-N operation with lower jitter as well as low power consumption.
  • Andrea Mazzanti (University of Pavia, Italy), Alessandro Franceschin (STMicroelectronics, Italy) and Domenico Riccardi (Infineon Technologies, Austria)
    BiCMOS (Voltage-Controlled) Oscillators with Ultra-Low Phase Noise
    This presentation reviews fundamental and technological limiting factors to the spectral purity of integrated RF oscillators and proposes circuit solutions to break the phase noise barrier in silicon technology. Phase noise can be scaled by resorting to the multi-core approach, provided mismatches among coupled oscillators are carefully considered. A 16-core 20 GHz (Voltage-Controlled) oscillator demonstrates −130 dBc/Hz at 1-MHz offset minimum phase noise with 850 mW from 2.4-V supply. A more elegant and efficient approach is then proposed. Leveraging the series resonance of a tank, the remarkably lower resistance rises considerably the tank active power, thus enabling a remarkable improvement on the spectral purity. Two 10GHz BiCMOS VCOs exploiting the concept are presented. The measured minimum phase noise is −138 dBc/Hz at 1-MHz offset with 600 mW from 1.2-V supply. Experimental results demonstrate the lowest phase noise ever reported by fully integrated RF oscillators in silicon technology.
  • Francesco Brandonisio (Maxlinear, Austria)
    Digital PLLs for WiFi: State-of-the-Art and Trends
  • Dmytro Cherniak (Infineon Technologies, Austria)
    Digitally-Intensive PLLs for mm-Wave FMCW Radars
    The vast number of FMCW radar applications generates the demand for highly-linear, low-noise and reconfigurable fast-chirp synthesizers implemented in high-volume deep sub-micron CMOS technologies. Conventional analog PLL-based chirp synthesizers realized in bipolar or BiCMOS technologies demonstrate an excellent phase noise performance, however, the modulation speed is typically limited by a narrow-bandwidth PLL. The emerging digital PLL-based synthesizers demonstrate prominent phase-noise and modulation-speed performance along with high degree of reconfigurability. This paper summarizes recent advances in digitally-intensive frequency synthesizers for mm-Wave FMCW radars implemented in deep sub-micron CMOS technologies.